The present invention relates to electronic systems with both analog and digital circuits, and in particular, to electronic systems with circuits that receive external signals and establish a data communications interface for controlling and configuring the analog and digital portions of the system.
One of the problems associated with electronic systems is the need to correct for non-idealities inherent in the analog portions of the system. For example, device mismatches in the analog sections of a system can cause voltage offsets that can have deleterious effects on the behavior the overall electronic system. Various non-idealities in analog systems and their corresponding impacts are known by those skilled in the art of analog circuit design. Analog circuit design is the art of precisely measuring and conditioning voltages and currents. The trend is always to amplify a signal with less noise, less offset, and more gain accuracy. To accomplish this, analog circuit designers have developed many building blocks: operational amplifiers, bandgap references, etc. But the quest to produce higher accuracy has led to a need for final adjustment of the circuit performance. In order to improve performance, various methods have been used to eliminate the effects of non-idealities. At the PCB (printed circuit board) level, potentiometer adjustment has been used for improve accuracy. Prior art methods implemented at the circuit level during production include various trimming techniques which are well known in the art, such as laser or current trimmable resistors or zener zapping. However, prior art trimming techniques are traditionally very expensive to implement during production and add to the cost of the electronic system.
Additionally, electronic systems can be designed to be reconfigured to perform different analog and digital functions. The systems are therefore useable in a range of applications. Such systems can be designed to receive signals which can reconfigure the system into different modes of operation.
Thus, there is a need for a way of eliminating non-idealities in analog circuits which can be cost effectively implemented during the production process. Additionally, there is a need for providing a data communication link which can be used for controlling and configuring the behavior and performance of the electronic system.
A system and method in accordance with the present invention provides for on-chip configuration, control and testing of mixed signal circuitry within an integrated circuit. A dual signal interface conveys the serial data and clock signals used for controlling the enablement, disablement and operational modes of the synchronous circuitry responsible for such on-chip configuration, control and testing, thereby minimizing the amount of overhead, in terms of interface terminals needed, for providing such capability.
In accordance with one embodiment of the present invention, an integrated circuit with mixed signal circuitry and configuration, control and testing circuitry for the mixed signal circuitry includes input terminals, interface terminals, interface circuitry, memory circuitry, analog circuitry and switching circuitry. The input terminals convey input signals including configuration control signals, while the interface terminals convey interface signals including analog interface signals. The interface circuitry, coupled to the input terminals, provides configuration data and switch control signals in response to the configuration control signals. The memory circuitry, coupled to the interface circuitry, stores the configuration data. The analog circuitry, coupled to the memory circuitry, includes internal and external circuit terminals, is electrically configurable and communicates internal and external analog signals via the internal and external circuit terminals, respectively, in response to a portion of the configuration data. The switching circuitry, coupled between the internal, external and interface terminals, alternately couples respective ones of the internal and external circuit terminals to corresponding ones of the interface terminals in response to the switch control signals. Respective ones of the internal and external analog signals change in response to corresponding changes in respective ones of the portion of configuration data.
In accordance with another embodiment of the present invention, control circuitry with a dual signal interface for controlling enablement and disablement of a synchronous system includes a data signal terminal, a clock signal terminal and an enablement control circuit. The data signal terminal conveys a serial data signal with first and second opposing signal states and first and second opposing signal transitions between the first and second opposing data signal states. The clock signal terminal conveys a clock signal with first and second opposing signal states and first and second opposing signal transitions between the first and second opposing clock signal states. The enablement control circuit, coupled to the data and clock signal terminals, provides a system enablement control signal with asserted and nonasserted signal states. An asserted system enablement control signal is provided in response to the data and clock signals following reception of a predetermined sequence of the first and second opposing data signal states and the first and second opposing clock signal state transitions, wherein the predetermined sequence includes: an initial first clock signal state transition coincident with the first data signal state; and coincidence of respective ones of the first and second opposing data signal states and the first and second opposing clock signal state transitions. A nonasserted system enablement control signal is provided in response to the first clock signal state having a duration greater than a predetermined interval.
In accordance with still another embodiment of the present invention, control circuitry with a dual signal interface for controlling the operational modes of a synchronous system includes a data signal terminal, a clock signal terminal and a mode control circuit. The data signal terminal conveys a serial data signal with first and second opposing signal states and first and second opposing signal transitions between the first and second opposing data signal states. The clock signal terminal conveys a clock signal with first and second opposing signal states and first and second opposing signal transitions between the first and second opposing clock signal states. The mode control circuit, coupled to the data and clock signal terminals, provides operation mode control signals with respective asserted and nonasserted signal states. An asserted operation mode control signal is provided in response to the data and clock signals following reception of a predetermined sequence of the first and second opposing data signal states and the first and second opposing clock signal state transitions, wherein the predetermined sequence includes: coincidence of the first clock signal state transitions with the second data signal state; and coincidence of respective ones of the first and second opposing data signal states and the second opposing clock signal state transitions. Nonasserted operation mode control signals are provided in response to the first clock signal state having a duration longer than a predetermined interval.
In accordance with yet another embodiment of the present invention, control circuitry with a dual signal interface for controlling enablement, disablement and the operational modes of a synchronous system includes a data signal terminal, a clock signal terminal, an enablement control circuit and a mode control circuit. The data signal terminal conveys a serial data signal with first and second opposing signal states and first and second opposing signal transitions between the first and second opposing data signal states. The clock signal terminal conveys a clock signal with first and second opposing signal states and first and second opposing signal transitions between the first and second opposing clock signal states. The enablement control circuit, coupled to the data and clock signal terminals, provides a system enablement control signal with asserted and nonasserted signal states. An asserted system enablement control signal is provided in response to the data and clock signals following reception of a predetermined sequence of the first and second opposing data signal states and the first and second opposing clock signal state transitions, wherein the predetermined sequence includes: an initial first clock signal state transition coincident with the first data signal state; and coincidence of respective ones of the first and second opposing data signal states and the first and second opposing clock signal state transitions. A nonasserted system enablement control signal is provided in response to the first clock signal state having a duration greater than a predetermined interval. The mode control circuit, coupled to the enablement control circuit and the data and clock signal terminals, provides operation mode control signals with respective asserted and nonasserted signal states. An asserted operation mode control signal is provided in response to the asserted system enablement control signal and the data and clock signals following reception of a predetermined sequence of the first and second opposing data signal states and the first and second opposing clock signal state transitions, wherein the predetermined sequence includes: coincidence of the first clock signal state transitions with the second data signal state; and coincidence of respective ones of the first and second opposing data signal states and the second opposing clock signal state transitions. Nonasserted operation mode control signals are provided in response to the first clock signal state having a duration longer than a predetermined interval, and in response to the nonasserted system enablement control signal.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.